|Port Type||Name||Width (bits)||Description|
This page provides detailed information about the SystemC TLM2 Fast Processor Model of the RISC-V RV64G core.
Processor IP owner is RISC-V Foundation. More information is available from them here.
OVP Fast Processor Model is written in C.
Provides a C API for use in C based platforms.
Provides a native C++ interface for use in SystemC TLM2 platforms.
The model is written using the OVP VMI API that provides a Virtual Machine Interface that defines the behavior of the processor.
The VMI API makes a clear line between model and simulator allowing very good optimization and world class high speed performance.
The model is provided as a binary shared object and is also available as source (different models have different licensing conditions). This allows the download and use of the model binary or the use of the source to explore and modify the model.
The model has been run through an extensive QA and regression testing process.
This model executes instructions of the target architecture and provides an interface for debug access. An interface to GDB is provided and this allows the connection of many industry standard debuggers that use the GDB/RSP interface. For more information watch the OVP video here.
The model also works with the Imperas Multicore Debugger and advanced Verification, Analysis and Profiling tools.
Model downloadable (needs registration and to be logged in) in package or1k.model for Windows32 and for Linux32
Model Variant name: RV64G
RISCV Family Processor Model.
Open Source Apache 2.0
This is early information on this model. Please contact Imperas for up to date information.
Currently being completed and verified.
OVP simulator downloadable (needs registration and to be logged in) in package OVPsim for Windows32 and for Linux32
OVP Download page here.
OVP documentation that provides overview information on processor models is available OVP_Guide_To_Using_Processor_Models.pdf.
Full model specific documentation on the variant RV64G is available OVP_Model_Specific_Information_riscv_RV64G.pdf.
Location: The Fast Processor Model source and object file is found in the installation VLNV tree: riscv.ovpworld.org/processor/riscv/1.0
Processor Endian-ness: This model can be set to either endian-ness (normally by a pin, or the ELF code).
Processor ELF Code: The ELF code for this model is: 0xf3
QuantumLeap Support: The processor model is qualified to run in a QuantumLeap enabled simulator.
The RV64G SystemC TLM2 Fast Processor Model also has parameters, model commands, and many registers.
The model may also have hierarchy or be multicore and have other attributes and capabilities.
To see this information, please have a look at the model variant specific documents.
Click here to see the detailed document OVP_Model_Specific_Information_riscv_RV64G.pdf.
Information on the RV64G OVP Fast Processor Model can also be found on other web sites::
www.ovpworld.org has the library pages http://www.ovpworld.org/library/wikka.php?wakka=CategoryProcessor
www.fast-models.com has the page www.fast-models.com/risc-v_models/rv64g
www.fast-cpu-models.com has the page www.fast-cpu-models.com/risc-v_models/rv64g
www.processor-models.org has the page www.processor-models.org/risc-v_models/rv64g
www.fast-processor-models.org has the page www.fast-processor-models.org/risc-v_models/rv64g
www.cpu-models.org has the page www.cpu-models.org/risc-v_models/rv64g
www.fast-core-models.org has the page www.fast-core-models.org/risc-v_models/rv64g
www.cpu-model-simulator.com has the page www.cpu-model-simulator.com/risc-v_models/rv64g
www.cpu-model-emulator.com has the page www.cpu-model-emulator.com/risc-v_models/rv64g
www.embedded-processor-models.org has the page www.embedded-processor-models.org/risc-v_models/rv64g
www.embedded-cpu-models.org has the page www.embedded-cpu-models.org/risc-v_models/rv64g
www.fast-model-tools-user-guide.com has the page www.fast-model-tools-user-guide.com/risc-v_models/rv64g
www.fast-iss-model.org has the page www.fast-iss-model.org/risc-v_models/rv64g
www.cpu-model-simulink.org has the page www.cpu-model-simulink.org/risc-v_models/rv64g
www.simulation-model.com has the page www.simulation-model.com/risc-v_models/rv64g
www.model-emulator.com has the page www.model-emulator.com/risc-v_models/rv64g
www.emulation-model.com has the page www.emulation-model.com/risc-v_models/rv64g
www.foundation-models.com has the page www.foundation-models.com/risc-v_models/rv64g
www.systemc-models.org has the page www.systemc-models.org/risc-v_models/rv64g
www.systemc-cpu-models.org has the page www.systemc-cpu-models.org/risc-v_models/rv64g
www.systemc-processor-models.org has the page www.systemc-processor-models.org/risc-v_models/rv64g
www.systemc-tlm-models.org has the page www.systemc-tlm-models.org/risc-v_models/rv64g
www.systemc-tlm-cpu-models.org has the page www.systemc-tlm-cpu-models.org/risc-v_models/rv64g
www.systemc-tlm-processor-models.org has the page www.systemc-tlm-processor-models.org/risc-v_models/rv64g
www.systemc-fast-models.org has the page www.systemc-fast-models.org/risc-v_models/rv64g
www.systemc-tlm-models-library.org has the page www.systemc-tlm-models-library.org/risc-v_models/rv64g
www.imperas.com has more information on the model library
http://www.ovpworld.org: Installation, Getting Started with OVP, and Cross-Compiling Applications
http://www.ovpworld.org: DEPRECATED: OVPsim Simulation Guide - Creating, Modifying, compiling and simulating platforms using
http://www.ovpworld.org: ARC Demo Video Presentation
http://www.ovpworld.org: Altera Nios II Bare Metal & Cyclone III Linux Booting Demo Video
Currently available Fast Processor Model Families.