Model Information

This page provides detailed information about the SystemC TLM2 Fast Processor Model of the Synopsys ARC synopsys_arc_synopsys (600) core.
This page is information about the Synopsys ARC_synopsys alias of the 600 variant.
Processor IP owner is Synopsys ARC. More information is available from them here.

OVP Fast Processor Model is written in C.
Provides a C API for use in C based platforms.
Provides a native C++ interface for use in SystemC TLM2 platforms.

The model is written using the OVP VMI API that provides a Virtual Machine Interface that defines the behavior of the processor.
The VMI API makes a clear line between model and simulator allowing very good optimization and world class high speed performance.

The model is provided as a binary shared object and is also available as source (different models have different licensing conditions). This allows the download and use of the model binary or the use of the source to explore and modify the model.

The model has been run through an extensive QA and regression testing process.

Embedded Software Development tools
This model executes instructions of the target architecture and provides an interface for debug access. An interface to GDB is provided and this allows the connection of many industry standard debuggers that use the GDB/RSP interface. For more information watch the OVP video here.
The model also works with the Imperas Multicore Debugger and advanced Verification, Analysis and Profiling tools.

Overview of Synopsys ARC synopsys_arc_synopsys (600) Fast Processor Model
Model Variant name: synopsys_arc_synopsys (600)
    ARC 600 processor model (ARCv1 architecture)
    Usage of binary model under license governing simulator usage. Source of model available under Imperas Software License Agreement.
    Instruction pipelines are not modeled in any way. All instructions are assumed to complete immediately.
    Instruction and data caches are not modeled, except for the auxiliary register interface.
    External host debug is not modeled, except for the auxiliary register interface.
    Real-world timing effects are not modeled. All instructions are assumed to complete in a single cycle.
    User extensions are not yet implemented, except for extension core registers.
    Models have been validated correct in a cooperative project between Imperas and ARC
    ARC Processor ARC6xx/ARC7xx Reference Documentation
    The model has been designed for debug using GNU gdb ARCompact/ARCv2 ISA elf32 version 7.5.1. To ensure correct behavior, enter the following command into gdb before attempting to connect to the processor:
     set architecture ARC600
    Failure to do this may cause the debugging session to fail because of g-packet size mismatch.
    The model implements the full ARCv1 instruction set.
    The model can be configured with either a 16-entry or 32-entry register file using parameter opt-rf16.
    The exact set of core instructions present can be configured by a number of parameters: see information for opt-swap, opt-bitscan, opt-extended-arith and opt-multiply in the table below.
    Parameter opt-extension-interrupts can be used to enable extension interrupts 16-31.
    Timer 0 and Timer 1 can be enabled using parameters opt-timer0 and opt-timer1, respectively.
    The versions of DCCM and ICCM build config registers can be specified using parameters opt-dccm-version and opt-iccm-version, respectively. The sizes of DCCM, ICCM0 and ICCM1 can be specified using parameters opt-dccm-size, opt-iccm0-size and opt-iccm1-size, respectively. Reset base addresses for the ICCMs can be specified using opt-iccm0-base and opt-iccm1-base. Note that the DCCM reset base address is architecturally defined (0x80000000) and not configurable. When CCMs are present, bus ports called DCCM0, ICCM0 and ICCM1 are created so that CCM contents may be viewed or modified externally by connecting to these ports. Parameter opt-internal-ccms specifies whether CCM memory is modeled internally or externally. If modeled externally, the CCMs must be implemented on a bus which is then connected to the CCM bus ports listed above (this parameter is ignored if CCM ports are unconnected; in that case, CCMs are always modeled internally). Parameter opt-reset-internal-ccms indicates that internally-modeled CCMs should be cleared to zero on a processor reset; if False, then internally-modeled CCMs retain their previous state after a reset.
    The set of core registers can be specified using parameter opt-extension-core-regs. This is a 64-bit value in which a 1-bit implies the presence of that core extension register. For example, a value of 0xf00000000ULL implies that extension registers r32-r35 should be configured.
    The reset value of the exception vector base register can be specified using parameter opt-intvbase-preset.

Model downloadable (needs registration and to be logged in) in package arc.model for Windows32 and for Linux32
OVP simulator downloadable (needs registration and to be logged in) in package OVPsim for Windows32 and for Linux32
OVP Download page here.
OVP documentation that provides overview information on processor models is available OVP_Guide_To_Using_Processor_Models.pdf.

Full model specific documentation on the variant synopsys_arc_synopsys (600) is available OVP_Model_Specific_Information_arc_600.pdf.

Location: The Fast Processor Model source and object file is found in the installation VLNV tree:
Processor Endian-ness: This model can be set to either endian-ness (normally by a pin, or the ELF code).
Processor ELF Code: The ELF code for this model is: 0x5d
QuantumLeap Support: The processor model is qualified to run in a QuantumLeap enabled simulator.

TLM Initiator Ports (Bus Ports)
Port TypeNameWidth (bits)Description
SystemC Signal Ports (Net Ports)
Port TypeNameDescription

No FIFO Ports in Synopsys ARC_synopsys.

Execution Modes
More Detailed Information

The Synopsys ARC_synopsys SystemC TLM2 Fast Processor Model also has parameters, model commands, and many registers.
The model may also have hierarchy or be multicore and have other attributes and capabilities.
To see this information, please have a look at the model variant specific documents.
Click here to see the detailed document OVP_Model_Specific_Information_arc_600.pdf.

Other Sites/Pages with similar information

Information on the Synopsys ARC_synopsys OVP Fast Processor Model can also be found on other web sites:: has the library pages has the page has the page has the page has the page has the page has the page has the page has the page has the page has the page has the page has the page has the page has the page has the page has the page has the page has the page has the page has the page has the page has the page has the page has the page has the page has more information on the model library

A couple of documents (from other related sites that might be of interest) Debugging Applications with GDB running on OVP platforms VMI Morph Time (VMI MT) API Reference Guide

Two Videos on these models (from other sites) Renesas v850 Bare Metal Video Presentation MIPS Demo Video Presentation

Currently available Fast Processor Model Families.

FamilyModel Variant
POWER Models    POWER Models aliases mpc82x UISA m476 m470 m460 m440 (aliases)
Renesas Models    Renesas Models aliases V850 V850E1 V850E1F V850ES V850E2 V850E2M V850E2R RH850G3M m16c r8c RL78-S1 RL78-S2 RL78-S3 (aliases)
RISC-V Models    RISC-V Models aliases RV32I RV32G RV64I RV64G (aliases)
MIPS Models    MIPS Models aliases ISA M14K M14KcTLB M14KcFMM 4KEc 4KEm 4KEp M4K 4Kc 4Km 4Kp 24Kc 24Kf 24KEc 24KEf 34Kc 34Kf 34Kn 74Kc 74Kf 1004Kc 1004Kf 1074Kc 1074Kf microAptivC microAptivP microAptivCF interAptiv interAptivUP proAptiv 5Kf 5Kc 5KEf 5KEc M5100 M5150 M6200 M6250 MIPS32R6 P5600 P6600 I6400 MIPS64R6 (aliases)
ARM Models    ARM Models aliases ARMv4T ARMv4xM ARMv4 ARMv4TxM ARMv5xM ARMv5 ARMv5TxM ARMv5T ARMv5TExP ARMv5TE ARMv5TEJ ARMv6 ARMv6K ARMv6T2 ARMv6KZ ARMv7 ARM7TDMI ARM7EJ-S ARM720T ARM920T ARM922T ARM926EJ-S ARM940T ARM946E ARM966E ARM968E-S ARM1020E ARM1022E ARM1026EJ-S ARM1136J-S ARM1156T2-S ARM1176JZ-S Cortex-R4 Cortex-R4F Cortex-A5UP Cortex-A5MPx1 Cortex-A5MPx2 Cortex-A5MPx3 Cortex-A5MPx4 Cortex-A8 Cortex-A9UP Cortex-A9MPx1 Cortex-A9MPx2 Cortex-A9MPx3 Cortex-A9MPx4 Cortex-A7UP Cortex-A7MPx1 Cortex-A7MPx2 Cortex-A7MPx3 Cortex-A7MPx4 Cortex-A15UP Cortex-A15MPx1 Cortex-A15MPx2 Cortex-A15MPx3 Cortex-A15MPx4 Cortex-A17MPx1 Cortex-A17MPx2 Cortex-A17MPx3 Cortex-A17MPx4 AArch32 AArch64 Cortex-A53MPx1 Cortex-A53MPx2 Cortex-A53MPx3 Cortex-A53MPx4 Cortex-A57MPx1 Cortex-A57MPx2 Cortex-A57MPx3 Cortex-A57MPx4 Cortex-A72MPx1 Cortex-A72MPx2 Cortex-A72MPx3 Cortex-A72MPx4 MultiCluster ARMv6-M ARMv7-M Cortex-M0 Cortex-M0plus Cortex-M1 Cortex-M3 Cortex-M4 Cortex-M4F (aliases)
Other Models    Other Models aliases Synopsys ARC_600 Synopsys ARC_605 Synopsys ARC_700 Synopsys ARC_0x21 Synopsys ARC_0x22 Synopsys ARC_0x31 Synopsys ARC_0x32 openCores_generic Xilinx MicroBlaze_V7_00 Xilinx MicroBlaze_V7_10 Xilinx MicroBlaze_V7_20 Xilinx MicroBlaze_V7_30 Xilinx MicroBlaze_V8_00 Xilinx MicroBlaze_V8_10 Xilinx MicroBlaze_V8_20 Xilinx MicroBlaze_V9_50 Xilinx MicroBlaze_V10_00 Xilinx MicroBlaze_ISA Altera Nios II_Nios_II_F Altera Nios II_Nios_II_S Altera Nios II_Nios_II_E (aliases)