|Port Type||Name||Width (bits)||Description|
This page provides detailed information about the SystemC TLM2 Fast Processor Model of the Synopsys ARC synopsys_arc_arc (600) core.
This page is information about the Synopsys ARC_arc alias of the 600 variant.
Processor IP owner is Synopsys ARC.
OVP Fast Processor Model is written in C.
Provides a C API for use in C based platforms.
Provides a native C++ interface for use in SystemC TLM2 platforms.
The model is written using the OVP VMI API that provides a Virtual Machine Interface that defines the behavior of the processor.
The VMI API makes a clear line between model and simulator allowing very good optimization and world class high speed performance.
The model is provided as a binary shared object and is also available as source (different models have different licensing conditions). This allows the download and use of the model binary or the use of the source to explore and modify the model.
The model has been run through an extensive QA and regression testing process.
This model executes instructions of the target architecture and provides an interface for debug access. An interface to GDB is provided and this allows the connection of many industry standard debuggers that use the GDB/RSP interface. For more information watch the OVP video here.
The model also works with the Imperas Multicore Debugger and advanced Verification, Analysis and Profiling tools.
Model downloadable (needs registration and to be logged in) in package arc.model for Windows32 and for Linux32. Note that the Model is also available for 64 bit hosts as part of the commercial products from Imperas.
Model Variant name: synopsys_arc_arc (600)
ARC 600 processor model (ARCv1 architecture)
Usage of binary model under license governing simulator usage. Source of model available under Imperas Software License Agreement.
Instruction pipelines are not modeled in any way. All instructions are assumed to complete immediately.
Instruction and data caches are not modeled, except for the auxiliary register interface.
External host debug is not modeled, except for the auxiliary register interface.
Real-world timing effects are not modeled. All instructions are assumed to complete in a single cycle.
User extensions are not yet implemented, except for extension core registers.
Models have been validated correct in a cooperative project between Imperas and ARC
ARC Processor ARC6xx/ARC7xx Reference Documentation
The model has been designed for debug using GNU gdb ARCompact/ARCv2 ISA elf32 version 7.5.1. To ensure correct behavior, enter the following command into gdb before attempting to connect to the processor:
set architecture ARC600
Failure to do this may cause the debugging session to fail because of g-packet size mismatch.
The model implements the full ARCv1 instruction set.
The model can be configured with either a 16-entry or 32-entry register file using parameter opt-rf16.
The exact set of core instructions present can be configured by a number of parameters: see information for opt-swap, opt-bitscan, opt-extended-arith and opt-multiply in the table below.
Parameter opt-extension-interrupts can be used to enable extension interrupts 16-31.
Timer 0 and Timer 1 can be enabled using parameters opt-timer0 and opt-timer1, respectively.
The versions of DCCM and ICCM build config registers can be specified using parameters opt-dccm-version and opt-iccm-version, respectively. The sizes of DCCM, ICCM0 and ICCM1 can be specified using parameters opt-dccm-size, opt-iccm0-size and opt-iccm1-size, respectively. Reset base addresses for the ICCMs can be specified using opt-iccm0-base and opt-iccm1-base. Note that the DCCM reset base address is architecturally defined (0x80000000) and not configurable. When CCMs are present, bus ports called DCCM0, ICCM0 and ICCM1 are created so that CCM contents may be viewed or modified externally by connecting to these ports. Parameter opt-internal-ccms specifies whether CCM memory is modeled internally or externally. If modeled externally, the CCMs must be implemented on a bus which is then connected to the CCM bus ports listed above (this parameter is ignored if CCM ports are unconnected; in that case, CCMs are always modeled internally). Parameter opt-reset-internal-ccms indicates that internally-modeled CCMs should be cleared to zero on a processor reset; if False, then internally-modeled CCMs retain their previous state after a reset.
The set of core registers can be specified using parameter opt-extension-core-regs. This is a 64-bit value in which a 1-bit implies the presence of that core extension register. For example, a value of 0xf00000000ULL implies that extension registers r32-r35 should be configured.
The reset value of the exception vector base register can be specified using parameter opt-intvbase-preset.
OVP simulator downloadable (needs registration and to be logged in) in package OVPsim for Windows32 and for Linux32. Note that the simulator is also available for 64 bit hosts as part of the commercial products from Imperas.
OVP Download page here.
OVP documentation that provides overview information on processor models is available OVP_Guide_To_Using_Processor_Models.pdf.
Full model specific documentation on the variant synopsys_arc_arc (600) is available OVP_Model_Specific_Information_arc_600.pdf.
Location: The Fast Processor Model source and object file is found in the installation VLNV tree: arc.ovpworld.org/processor/arc/1.0
Processor Endian-ness: This model can be set to either endian-ness (normally by a pin, or the ELF code).
Processor ELF Code: The ELF code for this model is: 0x5d
QuantumLeap Support: The processor model is qualified to run in a QuantumLeap enabled simulator.
The Synopsys ARC_arc SystemC TLM2 Fast Processor Model also has parameters, model commands, and many registers.
The model may also have hierarchy or be multicore and have other attributes and capabilities.
To see this information, please have a look at the model variant specific documents.
Click here to see the detailed document OVP_Model_Specific_Information_arc_600.pdf.
Information on the Synopsys ARC_arc OVP Fast Processor Model can also be found on other web sites::
www.ovpworld.org has the library pages http://www.ovpworld.org/library/wikka.php?wakka=CategoryProcessor
www.imperas.com has more information on the model library
http://www.ovpworld.org: Control File User Guide
http://www.ovpworld.org: VMI Memory Modeled Component (VMI MMC) API Reference Guide
Currently available Fast Processor Model Families.