Glossary

Bare Metal:          A platform with no operating system, often just a single processor with a fully populated memory space. Often the platform is used with a basic semihost library and referred to as a user-mode simulation.

Binary interception: The monitoring by a simulator of the execution of application code by a processor model so that the simulator can change its behavior without having to modify the application.

Core:                   Autonomous execution unit, usually defined by having its own program counter (PC).

Cycle Accurate Model: A model that represents the implementation details of a processor including its pipelines, and cycle by cycle state changes. (as opposed to Instruction Accurate)

Debug target:    Execution unit that is recognized by a debugger. Usually equivalent to a Core, but might not be.

DMI:                  Direct Memory Interface. (In TLM2.0) circumvention of the transaction mechanism, giving a processor model direct access to a memory model. When enabled this can speed up a simulation by orders of magnitude, but loses the ability to observe or analyze bus transactions.

Instance:          Copy of the part of a model that holds its state.  Some simulators can load a model once, then simultaneously simulate several instances without interference between them.

Instruction Accurate Model: A model that represents the functionality of a processors instruction execution without regard to artifacts like pipelines. Only instruction boundaries are visible. (as opposed to Cycle Accurate).

Instruction Set Simulator:  (ISS) A program that when run executes a model of a CPU allowing its instructions to be executed. Normally allows some connection to a debugger, and normally includes modeling of program/data memory and no peripherals.

MIPS:              Million Instructions Per Second. A measure of processor speed (not to be confused with MIPS Technologies, Inc, a  processor IP vendor).

Model:             Software simulation model of a processor or processor family.

Multicore:         A processor containing more than one core.

OVPsim:          Simulator that implements a subset  of the OVP APIs, available from the OVPworld website.

Platform:           Software model of a complete circuit comprising processors, memory, buses and peripherals. The simulation is accurate enough for software development but not for accurately predicting system performance..

Processor:        Indivisible device provided by a silicon vendor or licensor. Can be supplied as RTL, layout or finished silicon.

Quantum:          (In multiprocessor simulation) A time period in which each processor in turn simulates a certain number of instructions. Simulated time is advanced only at the end of a quantum, so this is limit of timing accuracy of the simulation. The quantum is usually fixed for the duration of a simulation, but can be changed (at the start of a new quantum).

Semihosting:     Interception by the simulator of calls in the application to I/O functions and the passing of the calls to the host operating system.

Sparse memory: Simulated memory is created by the OVP simulator as it is used; unused regions are not allocated. Therefore the simulator can create a model of a memory larger than that of the host computer.

TLB:                Translation Look-aside Buffer. Part of a processor’s VM controller.

Variant:            A configuration setting of a model to represent a specific vendor processor, for example to configure the generic MIPS model to be MIPS 24KEc.

Virtual Platform: as Platform.

VM:                 Virtual Memory or Virtual Memory controller. Hardware that allows a processor to simultaneously execute several programs without interfering with each other.

Multiprocessor Simulation:  Processors in multiprocessor platforms do not execute simultaneously; for efficiency each processor advances a certain number of instructions in turn. Increasing the number of instructions run on one processor in one turn (quantum) will reduce the time spent by the simulator switching context, so will improve simulation speed. However, it will also increase the chance that interactions between processors will be inaccurate with respect to the timing, especially if they communicate through shared memory. This mechanism is used in C, and C++, and SystemC TLM.0 platforms.


Currently available Fast Processor Model Families.

FamilyModel Variant
POWER Models    POWER Models aliases mpc82x UISA m476 m470 m460 m440 (aliases)
Renesas Models    Renesas Models aliases V850 V850E1 V850E1F V850ES V850E2 V850E2M V850E2R RH850G3M m16c r8c RL78-S1 RL78-S2 RL78-S3 (aliases)
RISC-V Models    RISC-V Models aliases RV32I RV32G RV64I RV64G (aliases)
MIPS Models    MIPS Models aliases ISA M14K M14KcTLB M14KcFMM 4KEc 4KEm 4KEp M4K 4Kc 4Km 4Kp 24Kc 24Kf 24KEc 24KEf 34Kc 34Kf 34Kn 74Kc 74Kf 1004Kc 1004Kf 1074Kc 1074Kf microAptivC microAptivP microAptivCF interAptiv interAptivUP proAptiv 5Kf 5Kc 5KEf 5KEc M5100 M5150 M6200 M6250 MIPS32R6 P5600 P6600 I6400 MIPS64R6 (aliases)
ARM Models    ARM Models aliases ARMv4T ARMv4xM ARMv4 ARMv4TxM ARMv5xM ARMv5 ARMv5TxM ARMv5T ARMv5TExP ARMv5TE ARMv5TEJ ARMv6 ARMv6K ARMv6T2 ARMv6KZ ARMv7 ARM7TDMI ARM7EJ-S ARM720T ARM920T ARM922T ARM926EJ-S ARM940T ARM946E ARM966E ARM968E-S ARM1020E ARM1022E ARM1026EJ-S ARM1136J-S ARM1156T2-S ARM1176JZ-S Cortex-R4 Cortex-R4F Cortex-A5UP Cortex-A5MPx1 Cortex-A5MPx2 Cortex-A5MPx3 Cortex-A5MPx4 Cortex-A8 Cortex-A9UP Cortex-A9MPx1 Cortex-A9MPx2 Cortex-A9MPx3 Cortex-A9MPx4 Cortex-A7UP Cortex-A7MPx1 Cortex-A7MPx2 Cortex-A7MPx3 Cortex-A7MPx4 Cortex-A15UP Cortex-A15MPx1 Cortex-A15MPx2 Cortex-A15MPx3 Cortex-A15MPx4 Cortex-A17MPx1 Cortex-A17MPx2 Cortex-A17MPx3 Cortex-A17MPx4 AArch32 AArch64 Cortex-A53MPx1 Cortex-A53MPx2 Cortex-A53MPx3 Cortex-A53MPx4 Cortex-A57MPx1 Cortex-A57MPx2 Cortex-A57MPx3 Cortex-A57MPx4 Cortex-A72MPx1 Cortex-A72MPx2 Cortex-A72MPx3 Cortex-A72MPx4 MultiCluster ARMv6-M ARMv7-M Cortex-M0 Cortex-M0plus Cortex-M1 Cortex-M3 Cortex-M4 Cortex-M4F (aliases)
Other Models    Other Models aliases Synopsys ARC_600 Synopsys ARC_605 Synopsys ARC_700 Synopsys ARC_0x21 Synopsys ARC_0x22 Synopsys ARC_0x31 Synopsys ARC_0x32 openCores_generic Xilinx MicroBlaze_V7_00 Xilinx MicroBlaze_V7_10 Xilinx MicroBlaze_V7_20 Xilinx MicroBlaze_V7_30 Xilinx MicroBlaze_V8_00 Xilinx MicroBlaze_V8_10 Xilinx MicroBlaze_V8_20 Xilinx MicroBlaze_V9_50 Xilinx MicroBlaze_V10_00 Xilinx MicroBlaze_ISA Altera Nios II_Nios_II_F Altera Nios II_Nios_II_S Altera Nios II_Nios_II_E (aliases)