Fast Processor Model of Renesas RL78 CPU Released by Imperas for Open Virtual Platforms

eSOL TRINITY, Imperas Partner, Developed the RL78 Model

Oxford, United Kingdom, May 31, 2016 - Imperas™ and eSOL TRINITY announced today the release of the Open Virtual Platforms™ (OVP™) Fast Processor Model for the Renesas RL78 CPU.  Example virtual platforms have also been released, as well as support for the new model in the Imperas M*SDK™ advanced software development tools.  The model of the RL78 was developed by eSOL TRINITY, Imperas’ partner in Japan, providing technical support for Imperas customers as well as services for embedded software development. 

The processor core model and example platforms are available from the Open Virtual Platforms website, www.OVPworld.org/Renesas.  The model of the RL78 processor core, as well as models of other Renesas processors, work with the Imperas and OVP simulators, including the QuantumLeap™ parallel simulation accelerator, and have shown exceptionally fast performance of hundreds of millions of instructions per second. 

“Our customers needed a fast model of the RL78 for software development and testing,” said Shuzo Tanaka, Vice President and Director (Tool Development and Sales) of eSOL TRINITY.  “We found the OVP technology to be very powerful and easy to use for development of the high performance RL78 processor core model.  The Imperas debug and software analysis and test products also provide an excellent software development environment. We are committed to help reduce time and cost for embedded software development with comprehensive solutions including Imperas products, technical support, and consultation and engineering services.”

All OVP processor models are instruction-accurate, and very fast, part of an embedded software development environment which is available early, so engineers can accelerate the entire product development cycle.  Virtual platforms utilizing these OVP processor models can be created with the OVP peripheral and platform models, or the processor models can be integrated into SystemC/TLM-2 based virtual platforms using the native TLM-2 interface available with all OVP processor models. 

The OVP models also work with the Imperas advanced tools for multicore software verification, analysis and debug, including key tools for hardware-dependent software development such as OS and CPU-aware tracing (instruction, function, task, event), profiling, code coverage and memory analysis. 

“The OVP APIs for model development were made public to allow users to develop, control and own their models and virtual platforms,” said Simon Davidmann, president and CEO of Imperas and founding director of the OVP initiative.  “It is great to see the OVP model library grow, and the Imperas ecosystem grow, through the development of publicly available models from our partners.” 

OVP also has the new Extendable Platform Kits™ (EPKs™) from Imperas, which are virtual platforms (simulation models) of the target devices, including the processor model(s) for the target device plus enough peripheral models to boot an operating system or run bare metal applications.  The platform and the peripheral models included in the EPKs are open source, so that users can easily add new models to the platform as well as modify the existing models.

About Imperas

For more information about Imperas, please see www.imperas.com.

About eSOL TRINITY

For more information about eSOL TRINITY, please see www.esol-trinity.co.jp.

All trademarks or registered trademarks are the property of Imperas Software Limited or their respective holders.

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ARM Cortex-A72 Models and Virtual Platforms Released by Imperas and Open Virtual Platforms

ARMv8 Support From Imperas Accelerates Embedded Software Development

Oxford, United Kingdom, May 24, 2016 - Imperas Software Ltd. (www.imperas.com), the leader in high-performance software simulation, announced the availability of models and virtual platforms for the Cortex-A72 ARMv8 processors, in addition to the previously released Cortex-A53 and A57 models.  This boosts the Imperas Open Virtual Platforms™ (OVP™) processor model library to over 160 models across a spectrum of IP vendors.  Over 40 ARM cores are supported including Cortex-A, Cortex-R and Cortex-M families.

Imperas support for ARMv8 cores, such as the Cortex-A72, includes models, Extendable Platform Kits™ (EPKs™), integration with ARM DS-5 for software debug and Linaro Linux booting on the virtual platforms.

Imperas Cortex-A72 ARM processor models are available in single-core, multi-core and multi-cluster configurations enabling high performance simulations of platforms ranging from simple single cores all the way to many core systems. Imperas has also built a model of the ARM GICv3 interrupt controller, which is available with the processor core models.

Extendable Platform Kits for ARMv8 processor cores running Linux are also available. EPKs are virtual platforms (simulation models) of the target devices, including the processor model(s) plus peripheral models sufficient to boot an operating system or run bare metal applications.  These EPKs, available for download from the OVP website, allow users to run high-speed simulations of ARM-based SoCs and platforms on any suitable PC. EPKs provide a base for users to extend and customize the functionality of the virtual platform, to closer reflect their own platform, by adding more component models, running different operating systems or adding additional applications. The platform and the peripheral models included in the EPKs are open source, so that users can easily add new models to the platform as well as modify the existing models.

These models and EPKs are part of the complete Imperas virtual platform environment for embedded software and hardware development and verification solutions.

Models of the ARM processor cores, as well as models of other processors, work with the Imperas and OVP simulators, and have shown exceptionally fast performance of hundreds of millions of instructions per second.  With the Imperas QuantumLeap™ parallel simulation accelerator, additional speed can be achieved for virtual platforms which include multiple processor instances, multicore processors and processors that support hardware multi-threading. This add-on to the Imperas simulator provides MPonMP™ (MultiProcessor target on MultiProcessor host) technology to take advantage of the multiple x86 cores in the host machine.  This can result, for example, in an increase in performance of 2.25x for a 4-core virtual platform with SMP architecture running on a 4-core host PC. 

OVP models also work with the Imperas advanced tools for multicore software development, verification, analysis and debug, including M*SDK™ advanced software development solutions and key tools for hardware-dependent software development such as OS and CPU-aware tracing (instruction, function, task, event), profiling, code coverage and memory analysis.  The tools utilize the Imperas SlipStreamer™ patent-pending binary interception technology.  SlipStreamer enables these analytical tools to operate without any modification or instrumentation of the software source code, i.e., the tools are completely non-intrusive.

“This release is just the latest in our line of ARMv8 processor models and EPKs, leveraging our advanced virtual platform technology. With these models and platforms, users can benefit from high performance simulation and embedded software development and test tools,” said Simon Davidmann, president and CEO of Imperas. 

For the latest list of ARM processor support, please see www.OVPworld.org.

About Imperas

For more information about Imperas, please see www.imperas.com.

All trademarks or registered trademarks are the property of Imperas Software Limited or their respective holders.

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prpl Security Group and Imperas Address IoT Security Challenges via Multi-Domain Virtualization

As a member of the prpl Foundation and its security working group, Imperas is working with several member who are using OVP technologies to develop and explore the use of hypervisors to improve device security, amongst other things.

In this article on EBN online, concern over automotive security is discussed and a hypervisor from SELTECH is introduced.

car hijacked using security breach

As a founding member of the Security Working Group of the prpl Foundation, Imperas is supporting the definition of a new open security framework for deploying secured and authenticated virtualized services in the Internet of Things (IoT) and related emerging markets.

Recent news shows that security is a key challenge to the wide scope and deployment of IoT, with varied consequences across many IoT markets. Imagine automotive hijacking. Power grid failure. Financial security breaches. Health care hacking. Consequences are severe: successful security measures in the IoT ecosystem will…

To read the full article click here.

To visit prpl click here.

Imperas Virtual Platform Based Software Tools at DAC and Embedded TechCon 2016

Linux Tutorial, Presentations on OS Porting and Software Development for ARM and Demos

OXFORD, United Kingdom, May 16, 2016 -- Imperas Software Ltd., the leader in high-performance software simulation, today announced their participation at the Design Automation Conference (DAC) 2016, inviting developers of electronic products to register for a demonstration of Imperas virtual platforms for embedded software and systems development, debug and test at the Imperas booth #839. Attendees can also register for the tutorial on Linux porting and bring up, delivered by Imperas. 

At the co-located Embedded TechCon conference, Imperas will be presenting papers on OS and driver development, and on the use of virtual platforms for software development targeted at ARM-based devices.

DAC is recognized as the premier conference for Electronic Design Automation (EDA), offering outstanding education, exhibits and networking opportunities for designers, researchers, tool developers and vendors. DAC attracts a worldwide community of more than 1,000 organizations, represented by system designers and architects, logic and circuit designers, validation engineers, software development engineers, CAD managers, senior managers and executives, and academicians.

Embedded TechCon, designed to educate today’s design engineers in the most critical embedded product and technologies, extends OpenSystems Media’s Embedded University. Classes, taught by leading industry experts, cover key embedded topics like IoT, automotive, and security as well as firmware development, debugging, and open-source hardware and software.

Where: Austin Convention Center, Austin, Texas.

When: DAC is June 5-9, 2016. Exhibits are open June 6-8, 2016. Embedded TechCon is June 7-8

HIGHLIGHTS:

  • DEMOS:  See Imperas virtual platform-based solutions for embedded software development, debug, analysis and verification demos in the Embedded Pavilion, booth #839.
    • Imperas demos will show a wide variety of Open Virtual Platforms (OVP) models and virtual prototypes including processor models of ARM (including Cortex-A,R and M families), Altera, Synopsys ARC, Imagination Technologies (MIPS), Renesas and Xilinx cores.
  • TUTORIALS: Imperas will deliver a tutorial on “Linux Porting and Bring Up, and Driver Development” featuring virtual platforms, as part of the System Software topic in the DAC Embedded Systems track.
    • Date: Monday, June 6, 2016
    • Time: 10:30am – 12:00pm
    • Location: 13AB
  • PRESENTATIONS at Embedded TechCon:
    • Pre-Silicon OS Porting, Bring Up and Driver Development
      • Date: Tuesday, June 7, 2016
      • Time: 2:00-2:25pm
      • Location: 13AB
    • Accelerating ARM Software Development, Debug and Test
      • Date: Tuesday, June 7, 2016
      • Time: 2:30-2:55pm
      • Location: 13AB

For more information, or to set up meetings with Imperas at DAC and Embedded TechCon, please email sales @ imperas.com

About Imperas

For more information about Imperas, please see www.imperas.com.

All trademarks or registered trademarks are the property of Imperas Software Limited or their respective holders.

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Automating System Design

The impact of the chip’s changing role in the system is becoming clearer.

Ann Steffora Mutschler of Semiconductor Engineering has written an interesting article on System Level design and its automation.

There are comments from Wally Rhines (chairman & CEO of Mentor), Simon Davidmann (president & CEO Imperas), Nandan Nayampally (VP marketing ARM), Nimish Modi (snr VP Cadence) and John Koeter (VP Synopsys).

Change is underway in the chip design world, creating opportunities and challenges that reach far beyond questions about whether Moore’s Law is slowing or stopping.

Never before in the history of semiconductors has design been so complex and sophisticated, and never has it touched so many lives in so many interesting ways. This is…

To read the article, click here.

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