Imperas to Demonstrate Renesas Device Virtual Platforms at Renesas DevCon 2015

Embedded Software Development, Debug and Test Solutions to be Shown

Oxford, United Kingdom, September 22, 2015 -- Imperas Software Ltd., the leader in high-performance software simulation and virtual platforms, today announced their participation at Renesas DevCon 2015. Highlights will include demonstrations of Imperas embedded software development, debug and test solutions at the Imperas booth in the exhibition area.  The demos will feature virtual platforms for the latest and most popular Renesas devices, including those based on both Renesas proprietary processor cores and those devices based on ARM cores, such as the RCar family and the recently announced Synergy family.

Imperas will also participate in a panel session, “Handling Software Development Complexity”, to take place at 4:30PM Monday, October 12.  Experts from across the industry will discuss how the development process, tools and architectures must change to handle the challenge of rapidly increasing software complexity.  Topics include how to engineer distributed functions, how to integrate multiple ECUs, development of advanced human-machine interfaces, adoption of advanced operating systems, separation of hardware and software, meeting ISO 26262, using model based approaches, and adopting  AUTOSAR.

For more information, or to set up meetings with Imperas at Renesas DevCon, please email sales@imperas.com

Renesas DevCon 2015 is an intensive four-day event filled with over 200 hours of lectures and labs, a solutions filled exhibit hall, and free development tools. You’ll also have the opportunity to learn from Renesas’ best and brightest during the one-on-one ‘Ask the Experts’ sessions, as well as interacting with the Renesas community and ecosystem. This is an exciting time to be part of this rapidly growing industry.

When: October 12-15, 2015.

Where: Hyatt Regency Orange County, CA.

We look forward to seeing you at this year’s DevCon!

About Imperas

For more information about Imperas, please see www.imperas.com.

All trademarks or registered trademarks are the property of Imperas Software Limited or their respective holders.

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prpl is Pragmatic for Security

Within the prpl Foundation Security Working Group, Imperas is providing solutions for embedded hypervisor/OS developers.

Simon Davidmann, Imperas CEO wrote a guest blog for RTC Magazine. RTC Magazine focusses on Embedded Computing and includes information for both hardware and software developers of embedded systems.

The article is about the security of embedded systems and what the prpl Foundation is doing about it, and what its Security Working Group is focussed on.

Most of the public discussion about security presents various aspects of the problems, or a high level view of risks/solutions, or an individual company’s solution to their slice of the problem. The prpl Foundation’s Security Working Group is taking a pragmatic, cross-functional approach to security in embedded devices and systems.

What do I mean by pragmatic and cross-functional? Let’s start by looking at the two primary…

Follow the link to read the full article.

 

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Five Questions for Simon Davidmann by Ann Steffora Mutschler of Semiconductor Engineering

Imperas’ CEO discusses challenges with software development and how things need to change.

Ann Steffora Mutschler sat down with Simon Davidmann, Imperas CEO, and discussed what software engineers want, software development challenges, software reuse, and software quality

The discussion was around five questions:

  • What do software engineers want today?
  • What are some of the biggest challenges that software engineers face today?
  • What about the notion of software reuse?
  • How can software be developed with a higher level of confidence that it is of higher quality?
  • What is the measurement of quality in software?

Follow the link to read the full article.

 

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Imperas Releases Second Generation of Open Virtual Platforms APIs and Adds to Free Model Libraries

Over 150 Fast Processor Models Now Available from the OVP Website

Oxford, United Kingdom, September 9th 2015 - Imperas today announces the release of the second generation of the Open Virtual Platforms™ (OVP™) APIs for building virtual platforms, additional Fast Processor Models, new models for popular peripherals and new Extendable Platform Kits™ (EPKs™).  Open Virtual Platforms is a website for the OVP APIs, for the OVP models and platforms, for the OVPsim simulator and for community discussion of virtual platforms on the OVP Forum.  The OVP APIs are publicly available and not proprietary, and the models and platforms are available under the Apache Open Source License.

New to OVP:

  • Support in the OVP APIs for unlimited hierarchy in virtual platform
  • Support in the OVP APIs for virtualized passing of packets between peripheral models
  • ARC EM6 model
  • SPARCv8 model (developed by Friedrich Alexander University)
  • CAN, ethernet and USB models
  • Altera Cyclone III Nios II Linux and Cyclone V HPS Cortex-A9MPx2 Linux EPKs
  • Freescale Kinetis Cortex-M4 MQX and Vybrid Cortex-A5 MQX EPKs
  • Xilinx MicroBlaze ML505 Linux

The addition of the ARC, ARM and SPARC Fast Processor Models brings the total number of CPU models available from OVP to over 150.  The performance for these models under a typical load is hundreds of millions of instructions per second, with peak performance of billions of instructions per second.  The library of fast processor models includes models of ARM processors from the ARMv4 through the ARMv8 architecture, a complete set of MIPS models, plus models of Altera Nios II, ARC, PowerPC, Renesas, SPARC and Xilinx MicroBlaze cores.  Models are available with both C (OVP) interface and a C++ (SystemC) interfaces.

Extendable Platform Kits are designed to help accelerate embedded software development, debug and test.  EPKs are virtual platforms (simulation models), including processor models plus peripheral models necessary to boot an operating system (OS) or run bare metal applications.  The platform and peripheral models included in the EPKs are open source, so that users can easily add new models to the platform as well as modify the existing peripheral models.  The example OS and/or applications are also included. 

OVP models work with both the OVPsim and the Imperas simulators, including the QuantumLeap parallel simulation accelerator.  OVPsim is used for academic and other non-commercial users (over 1,000 university departments current subscribe to the OVP website), while the Imperas products are for commercial users.  Imperas M*SDK includes the OVP model library, iGen for model development, support for heterogeneous, multiprocessor / multicore processors, a comprehensive Verification, Analysis, and Profiling (VAP) tool set, plus an advanced 3-dimensional (temporal, spatial and abstraction) debug solution, 3Debug™, for heterogeneous multicore processor, peripheral, and embedded software debug.  The VAP tool suite contains more than 50 tools supporting hardware-dependent software development, including OS and CPU-aware tracing (instruction, function, task, event), profiling, code coverage and memory analysis.  The Imperas SlipStreamer™ patent-pending binary interception technology enables these analytical tools to operate without any modification or instrumentation of the software source code, i.e., the tools are completely non-intrusive.

“OVP is becoming the de facto source for models of processors,” said Simon Davidmann, president and CEO of Imperas.  ”Additional models and platforms have been contributed by the user community, and now the OVP ecosystem is at the cutting edge of embedded software development.”

About Imperas

For more information about Imperas, please see www.imperas.com.

All trademarks or registered trademarks are the property of Imperas Software Limited or their respective holders.

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