What Is A System Now in Semiconductor Engineering by Ann Steffora Mutschler

In a recent article in Semiconductor Engineering, Ann Steffora Mutschler states that as designs become part of connected networks, so do the requirements for what’s needed to make it work properly.

Defining a system used to be relatively straightforward. But as systems move onto chips, and as those chips increasingly are connected with applications and security spanning multiple devices, the definition is changing.

This increases the complexity of the design process itself, and it raises questions about how chips and software will be designed and defined in the age of the Internet of Things/Everything. For example, will engineers be developing software-defined hardware, network-defined software and hardware, or application-driven connected systems?

Simon Davidmann, CEO of Imperas, asserts that the classical definition of an electronic ‘system’ still stands—a product composed of both hardware and software components. “But what constitutes a typical ‘system’ has evolved considerably, especially software content, so the technologies and methodologies that are used to develop, debug and test the system become critically important.”

To this point, he noted the dramatic increase in software content in systems over the last 10 years. “The ratio of software to hardware engineers is…

Follow the link to read the full article.



Fast Processor Models of ARM Cores Released by Imperas with Changes to OVP ARM Core Model Licensing Terms

Imperas Open Virtual Platforms Accelerate Embedded Software Development for Multi-Core ARM-based Designs

Oxford, United Kingdom, June 8th 2015 – Imperas™ today announces the release of Open Virtual Platforms™ (OVP™) Fast Processor Models for popular ARM® cores: Cortex®-A17, Cortex®-M0, Cortex®-M0+, and Cortex®-M1. Also announced are changes to the terms of licensing of the OVP ARM Models.

New Extendable Platform Kits™ (EPKs™) of ARM-based devices are available from Imperas, working together with the M*SDK™ tools, to help accelerate embedded software development, debug and test.  EPKs are virtual platforms (simulation models), including processor models plus peripheral models necessary to boot an operating system (OS) or run bare metal applications.  The platform and peripheral models included in the EPKs are open source, so that users can easily add new models to the platform as well as modify the existing peripheral models.  The example OS and/or applications are also included.

Imperas M*SDK solutions are complete embedded software development environments, including virtual platforms. They are specifically designed to handle complex multi-core issues. M*SDK contains an OVP model library, iGen for model development, support for heterogeneous, multiprocessor/ multicore processors, a comprehensive verification, analysis, and profiling (VAP) tool set, plus an advanced 3-dimensional (temporal, spatial and abstraction) debug solution, 3Debug™, for heterogeneous multicore processor, peripheral, and embedded software debug. Imperas solutions support hardware-dependent software development such as OS and CPU-aware tracing (instruction, function, task, event), profiling, code coverage and memory analysis.  The Imperas SlipStreamer™ patent-pending binary interception technology enables these analytical tools to operate without any modification or instrumentation of the software source code, i.e., the tools are completely non-intrusive.

Currently the following virtual platform EPKs using OVP ARM models are available: Versatile Express Cortex-A9MP Linux, Versatile Express Cortex-A15MP Linux, Integrator CP Cortex-A9UP Linux, Integrator CP Nucleus, Integrator CP eCos, ARMv8-A-FMv1 Cortex-A57MP Linaro Linux, Cortex-M3 uCosII, Cortex-M3 freeRTOS, openRTOS, Altera Cyclone V HPS Cortex-A9MPx2 Linux, Freescale Kinetis Cortex-M4 MQX.

The processor core models and OVP-based virtual platforms are available from the Open Virtual Platforms website, http://www.OVPworld.org/ARM.  Models of these ARM cores, as well as other models, work with the Imperas and OVP simulators, including the QuantumLeap™ parallel simulation accelerator, and have shown exceptionally fast performance of hundreds of millions of instructions per second.
Currently available OVP models of the latest ARM cores include: Cortex-A5UP, Cortex-A5MP, Cortex-A7UP, Cortex-A7MP, Cortex-A8, Cortex-A9UP, Cortex-A9MP, Cortex-A15UP, Cortex-A15MP, Cortex-A17UP, Cortex-A17MP, Cortex-A53MP, Cortex-A57MP, AArch32, AArch64, Cortex-M0, Cortex-M0+, Cortex-M1, Cortex-M3, Cortex-M4, Cortex-M4F, Cortex-R4, Cortex-R4F. (See OVPworld.org/ARM for the complete list and more information.)

“ARM cores, with state-of-the-art features such as TrustZone and hardware virtualization, require state-of-the-art software development tools,” said Simon Davidmann, president and CEO of Imperas.  “Imperas virtual platform solutions help our users realize positive ROI very quickly, with higher quality software, and accelerated software development schedules.”

The May 2015 OVP release of OVP ARM core models provides only the binaries of the models. Open source of these models is no longer available. The source of the OVP ARM core models can be obtained under license from Imperas. Also, changes have been made to the terms of the licensing of the OVP ARM core models, please see OVPworld.org/about_licensing for more details.

About Imperas

For more information about Imperas, please see www.imperas.com.

All trademarks or registered trademarks are the property of Imperas Software Limited or their respective holders.

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OS bring up using virtual platforms in Imagination Blogs by Larry Lapides

Larry Lapides of Imperas recently posted a guest blog at the Imagination MIPS processor blog site. it discusses topics related to Operating System bring up and how virtual platform and advanced tools can provide signiificant benefits.

Linux has become the general purpose operating system of choice for embedded systems, and is almost always supported for high end SoCs developed by semiconductor vendors.  These SoCs now have multicore processors, and run symmetric multiprocessor (SMP) Linux. Most vendors start with the MIPS Linux distribution, then customize it for the specific SoC (requiring device tree changes), including the necessary drivers for the peripherals on the SoC as well as supporting other customizations and unique features. While the MIPS Linux distribution is a great starting point, that does not make customization and bring up an easy task.

To put it another way:  Just because you get to the Linux prompt doesn’t mean everything is working.

Just where do virtual platforms fit in this?

Instruction accurate virtual platforms, which are …

To read the full blog, please visit the Imagination Blog Site.


FlexTiles Adaptive Multicore SoC Virtual Platform Now Available from Imperas

Imperas Technologies Used for FlexTiles Program

Oxford, United Kingdom, 2 June 2015 - Imperas Software Ltd. (www.imperas.com), the leader in high-performance software simulation, today announced that a virtual platform for the FlexTiles platform is now available, based on Imperas™ and Open Virtual Platforms™ (OVP™) simulators and models. 

The FlexTiles platform is a self-adaptive heterogeneous multicore 3D System-on-Chip (SoC) architecture developed by a consortium of universities, research institutes and commercial companies, with funding from the European Union under the Seventh Framework Programme. A major challenge in computing is to leverage multicore technology to develop energy-efficient high-performance systems. This is critical for embedded systems with a very limited energy budget, as well as for supercomputers in terms of sustainability. Moreover, the efficient programming of multicore architectures is critical, especially with more than a thousand cores per SoC predicted by 2020.  These challenges were the drivers for the FlexTiles project.

The FlexTiles project has developed an energy-efficient, programmable many-core platform with self-adaptive capabilities, along with an innovative virtualization layer and a dedicated tool flow. As similar architectures are adopted in industry, improvements in programming efficiency, and therefore reductions in time to market, are expected, together with a reduction in overall development costs of 20 to 50%.

The project successfully used the OVP technologies to create a many-core virtual platform, which is available at no cost from Karlsruhe Institute of Technology (KIT), and from the OVP Library page for KIT.  Imperas simulation and OVP models were selected because of superior performance and the availability of open source models.  While the FlexTiles architecture is not processor-specific, the Xilinx MicroBlaze was used to demonstrate the capabilities of the architecture, both in demo hardware and in the virtual platform.

“M*SDK™, the OVP APIs and the OVP library of models have been a great asset to the FlexTiles project, enabling us to quickly create a virtual platform for our advanced architecture,” stated Stephan Werner of Karlsruhe Institute of Technology.  “We were able to use the Imperas technology and tools to develop multiple demonstrations of the FlexTiles architecture, including multiple hardware configurations, the Network on Chip (NoC) developed in this project and the operating system and software tools for FlexTiles.”

Simon Davidmann, CEO of Imperas, said: “The FlexTiles project is visionary, and Imperas has been pleased to support it, both during the development phase and now with the distribution of the virtual platform. For a project with this level of many-core scalability, high performance simulation and models are key.”

Dave Tokic, Senior Director of Partner Ecosystems at Xilinx, commented:  “We’re excited to see Xilinx FPGAs, including the MicroBlaze cores, used in a project with such far-reaching impact.  High performance processor models, virtual platforms and software development tools, such as are available from Imperas and OVP, are critical to the quality and success of embedded software projects.”

About Imperas
For more information about Imperas, please go to www.imperas.com.

Imperas, Open Virtual Platforms, Extendable Platform Kits, EPKs, QuantumLeap, MPonMP, OVP, OVPsim, M*SDK, C*DEV, S*DEV, M*DEV, iGen, iGui, ToolMorphing and SlipStreamer are trademarks of Imperas Software Limited. Imperas acknowledges trademarks or registered trademarks of other organizations for their respective products and services.

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