CDNLive, 11-12 March 2014, Santa Clara, California. Imperas Presenting a paper on the importance of simulation speed for software quality

CDNLive is March 11-12 in Santa Clara, California and is organized by Cadence Design Systems.  Imperas will be presenting a paper titled “Software Quality is Directly Proportional to Simulation Speed” as part of Track 6, at 4pm Tuesday March 11th.  Here is the abstract: 

“Software quality is directly proportional to simulation speed.”  This is obvious, even intuitive, for engineers.  Faster simulations mean more tests can be run, which in turn means more bugs can be found, which results in higher quality.  Reduced schedules can be a side benefit of speed. 

While this is obvious, why is it so important right now?  One example is server SoCs, where software/systems test suites can include hundreds of tests, each consisting of hundreds of billions of instructions.  If the virtual platform performance is 100 MIPS, this test suite could take over one week to run.  If the performance is five times faster, running the test suite takes 1 day; ten times faster and it runs overnight.  This simulation speed is especially interesting with the new generation of ARMv8 based server SoCs.  It is also interesting in areas such as image recognition, where hardware accelerators sit next to the CPUs on the SoC. 

In this paper we will discuss virtual platform simulation performance, including how to take advantage of the multiple cores on the host PC for increased simulation speed.  Examples of virtual platforms with 1) ARMv8 multicore processors and 2) hardware accelerators will be shown to illustrate how simulation speed can be accelerated.

DVCon, 3-6 March 2014, San Jose, California. Imperas present paper

DVCon is March 3-6 in San Jose, California.  Imperas will be presenting a paper titled “Learning From Advanced Hardware Verification for Hardware Dependent Software” as part of Session 3, at 9:30am Tuesday March 4th.  Here is the abstract: 

We present a new perspective for embedded software verification for generalized multicore processor platforms, somewhat analogous to simulation-centric hardware verification solutions. A spatial, temporal, and abstract multi-dimensional framework for software verification, profiling, analysis, and debug is proposed that leverages a specialized simulation core. The simulator enables key services for the verification solution while providing a degree of separation from both the hardware models and software under test, to ensure accurate behavioral representation, as well as customization and performance advantages.

This paper will discuss requirements for modern embedded software development and solutions utilized to date, before discussing this simulation-based solution and the dimensional framework layered above. We will also discuss two real life scenarios where the solution is utilized to affect.

Embedded World, 25-27 Feb 2014, Nuremberg, Germany. Imperas present paper, demos in partner booths

Embedded World is February 25-27 in Nuremberg, Germany.  Imperas will be presenting a paper titled “Customized, Intelligent Memory Access Monitoring for Reliable Asymmetric MultiProcessor System Development” in Session 23, Thursday at 14:00.  We will be available for demos of the Imperas simulation and software development, debug and test tools in the Altera booth Tuesday and Wednesday from 10:00-11:00 and 14:00-15:00, and Thursday from 10:00-11:00.  We will also be in the Imagination Technologies booth for demos of the Imperas tools for MIPS cores.

Here is a brief summary of the paper: 

The use of Asymmetric MultiProcessor (AMP) architectures is now widespread.  Two common implementations are Linux running on one core of a dual-core ARM Cortex-A9, with an RTOS running on the other, and SMP Linux running on the dual-core ARM Cortex-A9 and an RTOS or bare metal application running on another processor core, such as an Altera NIOS II. The reliability of such a system is highly dependent on the correct functioning of inter-core interaction with shared resources, which is often hard to verify. 

This paper will detail the methodology used to bring up such an AMP system on a virtual platform.  The first step is the construction of the instruction accurate virtual platform for the two AMP systems.  The Open Virtual Platforms APIs for model and platform development are used in building the virtual platforms used in this paper.  These virtual platforms are variants of the Altera SoC FPGA Cyclone V product.  The second step in the process involves the use of CPU- and OS-aware analysis tools to help with initial system bring up.  Rather than providing only instruction trace data, these tools enable the analysis of the system at the appropriate level of abstraction for the software engineer:  C source code for firmware and drivers and the OS task/event level for operating systems.  In addition, the tools are non-intrusive, requiring no instrumentation or modification of the application or OS, thus validating the results of the analysis. 

Finally, the third step is the development of a robust test environment, including the use of non-intrusive, intelligent memory access monitors, built upon the CPU- and OS- aware simulation environment to ensure that different OS operations do not access forbidden memory segments.

A detailed case study illustrating how complex faults have been found in an Altera Cyclone V AMP system, by using this methodology, will be shown.

Imperas Supports Imagination MIPS Cores With Fastest Ever Processor Model Simulation

QuantumLeap parallel simulation accelerator enables virtual platform performance of greater than 16 billion instructions per second, the fastest commercial solution available today

Oxford, United Kingdom, February 4th, 2014 - Imperas Software Ltd. (www.imperas.com), the leader in high-performance software simulation, has added support for models of Imagination Technologies’ MIPS processors to QuantumLeap™, a parallel simulation performance accelerator.

QuantumLeap leverages Imperas’ new synchronization algorithm to provide the fastest virtual platform software execution speed available today on standard, multi-core Personal Computer (PC) host machines.  The Imperas technology – simulation plus processor core models – provides the MIPS ecosystem with the fastest software simulation solution in the industry. 

The Imperas Open Virtual Platforms (OVP) models support the new architectural features of the MIPS Series5 Warrior generation of cores from Imagination.  These new features include SIMD (Single Instruction Multiple Data) operations with the MIPS SIMD Architecture (MSA) and hardware virtualization, key features of the new MIPS Warrior cores.  The high-performance P-class P5600 has already been announced, with  entry-level M-class cores and mid-range I-class cores to come later this year and broaden the Warrior generation lineup.  Imagination and Imperas are collaborating on the development of the OVP processor core models to ensure the highest quality models for the MIPS community.  The Imperas simulators support virtual platforms with both homogeneous processor cores, as well as heterogeneous platforms, for example with both the MIPS P5600 and other Imagination IP cores present. 

"We're delighted to be working with Imperas to deliver the fastest Instruction Accurate (IA) simulation solution for our many MIPS partners,” said Tony King-Smith, EVP of marketing for Imagination Technologies. “We’ve been impressed how Imperas’ simulation technology significantly outperforms other commonly-used solutions. Faster simulation results in more tests being run, and therefore higher quality software being developed – and that’s good news for our extensive MIPS ecosystem community.  Since acquiring MIPS, Imagination has committed to working more closely with innovative partners like Imperas to deliver superior CPU modelling solutions. As a result, we’re confident our MIPS licensees and many software ecosystem partners will have access to the best tools in the industry, enabling them to create the best possible software and products.””  

In the server, home entertainment and mobile markets, most current System-on-Chip (SoC) devices incorporate multicore embedded processors coupled with hardware accelerators, all executing in parallel.  The performance of existing, single-threaded virtual platform simulators does not adequately scale for these SoCs, creating a barrier to efficient virtual platform-based software development, debug and test.

Imperas Simulation Technology Performance Innovation

QuantumLeap eliminates this barrier by allocating the simulated cores across all the processors in a host machine. By ensuring the efficient synchronization of these cores, near linear scaling of the simulation across the multiple host processors has been observed, with the impact of inter-core communication kept to a minimum. Furthermore, QuantumLeap provides a transparent use model, with no change required to the software-under-test, the virtual platform models or the development environment, while ensuring fully deterministic simulation execution.  The execution performance of this new technology has been measured on average at 15 times faster than the nearest commercial solution using standard benchmarks, running on a standard 3.4 GHz quad core host PC.

Software quality is directly proportional to simulation speed,” noted Simon Davidmann, CEO of Imperas.  “With QuantumLeap, we have enabled our users to take a significant step, a leap if you will, in embedded software testing.”

QuantumLeap allows full access to the Imperas Multi-core Software Development Kit (M*SDK) verification capabilities.  The accelerator includes the ToolMorphing and SlipStreamer™ capabilities, such that the full tool suite operates with minimal impact to performance and no adverse affect on simulated software operation.  QuantumLeap operates on platforms that incorporate both Asymmetric Multi-Processing (AMP) and Symmetric Multi-Processing (SMP) schemes.  It has been designed to effectively handle the inter-core communication overhead challenges associated with the most complex SMP processor architectures including, for example, devices based on the state-of-the-art Imagination MIPS Warrior P5600 multi-core processors.

About Imperas

Imperas Software was founded in 2008 to develop and deliver embedded software development systems. The company’s comprehensive product line enables the rapid creation of high-performance virtual platforms and the efficient development of embedded software utilizing those platforms. Imperas’ technology allows for software engineering schedules to be significantly reduced while improving the quality of products relying on embedded systems. In 2008 Imperas founded the Open Virtual Platforms (OVP) consortium to improve the availability of open model libraries and virtual platform infrastructure. Leading communications, automotive, consumer electronics and embedded processor companies rely on Imperas for the development of their electronic products. The company’s corporate headquarters is located near Oxford, UK and it maintains support and sales organizations in Silicon Valley, California and Tokyo, Japan. For more information about Imperas, please go to www.imperas.com.

Imperas, Open Virtual Platforms, QuantumLeap, OVP, OVPsim, M*SDK, C*DEV, S*DEV, M*DEV, ToolMorphing and SlipStreamer are trademarks of Imperas Software Limited. Imperas acknowledges trademarks or registered trademarks of other organizations for their respective products and services.

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