Imperas Delivers QuantumLeap Simulation Synchronization Industry First Parallel Virtual Platform Simulator

Parallel synchronization technology augments existing high-performance simulator to accelerate virtual platforms beyond 16,000 MIPS, the fastest commercial solution available today

Oxford, United Kingdom, October 22nd, 2013—Imperas Software Ltd. (www.imperas.com), the leader in high-performance software simulation, has released QuantumLeap™, a parallel simulation performance accelerator. QuantumLeap leverages a new synchronization algorithm to provide the fastest virtual platform software execution speed available today on standard, multi-core Personal Computer (PC) host machines.

The execution performance of this new technology has been measured on average at 15 times faster than the nearest commercial solution using standard benchmarks.

Many current System-on-Chip (SoC) hardware platforms, for example mobile and server devices, incorporate multi-core embedded processors coupled with hardware accelerators, all executing in parallel. The performance of existing, single-threaded virtual platform simulators does not adequately scale for these SoCs, creating a barrier to efficient virtual platform-based software development.

QuantumLeap eliminates this barrier by allocating the simulated cores across all the processors in a host machine. By ensuring the efficient synchronization of these cores, near linear scaling of the simulation across the multiple host processors has been observed, with the impact of inter-core communication kept to a minimum. Furthermore, QuantumLeap provides a transparent use model, with no change required to the software-under-test, the virtual platform models or the development environment, while ensuring fully deterministic simulation execution.

“The serial simulation of today’s embedded, multi-core SoCs is totally impractical for rigorous software verification, even given the abstraction provided through current virtual platform simulation techniques,” notes Simon Davidmann, CEO of Imperas. “We have solved this with QuantumLeap, which can simulate a multi-core ARM® Cortex™-A9 platform running standard benchmarks at execution speeds up to 16 Billion Instructions-Per-Second running on a standard 3.4 GHz quad core host PC, an astounding result by any measure.”

Imperas Simulation Technology Performance Innovation
Imperas’ simulation technology is based on a Just-In-Time (JIT) Code Morphing engine that streams simulation execution to maximize performance, providing the fastest software processor models available today. The company’s ToolMorphing™ algorithm further extends this capability by neutralizing the performance impact of the running of software verification tools within simulation.

The QuantumLeap accelerator extends this approach to include parallel engine execution, spreading a virtual platform simulation across multiple host PC processors. QuantumLeap’s proprietary synchronization algorithm minimizes the impact of communication between the parallel cores, allowing them to scale across available host PC processors as much as possible.

QuantumLeap operates on platforms that incorporate both Asymmetric Multi-Processing (AMP) and Symmetric Multi-Processing (SMP) schemes. It has been designed to effectively handle the inter-core communication overhead challenges associated with the most complex SMP processor architectures including, for example, devices based on the state-of-the-art ARM Cortex-A57 and Imagination MIPS Warrior P5600 multi-core processors.

QuantumLeap allows full access to the Imperas Multi-core Software Development Kit (M*SDK) verification capabilities. The accelerator includes the ToolMorphing and SlipStreamer™ capabilities, such that the full tool suite operates with minimal impact to performance and no adverse affect on simulated software operation. QuantumLeap also operates with the full Open Virtual Platforms™ (OVP™) model library, allowing the entire, 125+ range of processor models to be accelerated.

“Our customers need to develop and deliver bug free, high quality embedded software in their products, and to achieve this many employ large regression test environments continuously throughout code development,” continued Davidmann. “QuantumLeap can dramatically change their engineering operation by enabling full execution of multi-trillion instruction regression tests every night to ensure the highest possible software quality and shave months off their schedules.”

Availability
The QuantumLeap accelerator is available immediately, with pricing provided upon application. The full range of Imperas technology, including QuantumLeap, will be demonstrated in the Imperas booth, number 520, at ARM TechCon, October 29–31, 2013. Benchmark information is also available at the Imperas website.

 

QuantumLeap Chart

About Imperas
Imperas Software was founded in 2008 to develop and deliver embedded software development systems. The company’s comprehensive product line enables the rapid creation of high-performance virtual platforms and the efficient development of embedded software utilizing those platforms. Imperas’ technology allows for software engineering schedules to be significantly reduced while improving the quality of products relying on embedded systems. In 2008 Imperas founded the Open Virtual Platforms (OVP) consortium to improve the availability of open model libraries and virtual platform infrastructure. Leading communications, automotive, consumer electronics and embedded processor companies rely on Imperas for the development of their electronic products. The company’s corporate headquarters is located near Oxford, UK and it maintains support and sales organizations in Silicon Valley, California and Tokyo, Japan. For more information about Imperas, please go to www.imperas.com.

Imperas, Open Virtual Platforms, QuantumLeap, OVP, OVPsim, M*SDK, C*DEV, S*DEV, M*DEV, ToolMorphing and SlipStreamer are trademarks of Imperas Software Limited. Imperas acknowledge trademarks or registered trademarks of other organizations for their respective products and services.

# # #

Altera Nios II Processor Model Delivered By Imperas

Open source simulation model enables Altera customers to more easily validate and debug Nios II embedded software

San Jose, Calif., October 22nd, 2013—Imperas Software Ltd. (www.imperas.com), founder of the Open Virtual Platforms™ (OVP™) consortium, today announced the availability of the Altera Nios II embedded processor OVP model. Jointly developed by Imperas and Altera, this open source model will enable a high-performance development environment for Nios II embedded software.

The OVP Fast Processor Model of the Nios II may be configured at start-up to match the intended behavior of the actual FPGA component, but will execute significantly faster than real-time. This allows embedded software to be tested more rigorously and earlier in the design process, accelerating complex software development cycles.

“Imperas led formation of the Open Virtual Platforms consortium to improve the embedded software development experience,” said Simon Davidmann, CEO of Imperas. “With Altera, we have taken an important step today by providing designers with a high-performance model of the Altera Nios II processor, executing many times faster than other development offerings to enable the most comprehensive software verification solution available.”

The model and underlying simulator includes a comprehensive application program interface (API) that extends visibility into the processor behavior. This allows the designer to run embedded software, either from Altera or their own code, and leverage advanced analysis and debug operations, including operating system awareness.

“Engineers are seeking rapid development methods that also provide immediate feedback on configuration or customization, said Premal Buch, vice president, Software Engineering, Altera. “The Altera Nios II device has been the most widely used FPGA-based processor for many years, and this OVP model will help customers expand their design options.”

The complexity of system modeling in multi-core and multi-processor environments is driving the need for advanced virtual platform development and verification environments. Verification technologies that operate at a range of abstractions, including CPU- and OS-Aware levels, and that can provide customizable operations that work intimately with the design, are required. The performance of these systems will become more critical as the volume of tests required increase.

The new model of Altera’s Nios II processor will be showcased in the Imperas booth, number 520, at ARM TechCon, October 29–31, 2013.

Availability
The Altera Nios II OVP processor model is available now, and may be downloaded from the OVP website: www.OVPworld.org/Nios_II.

About Imperas and OVP
Imperas Software was founded in 2008 to develop and deliver embedded software development systems. The company’s comprehensive product line enables the rapid creation of high-performance virtual platforms and the efficient development of embedded software utilizing those platforms. Imperas’ technology allows for software engineering schedules to be significantly reduced while improving the quality of products relying on embedded systems. In 2008 Imperas founded the Open Virtual Platforms (OVP) consortium to improve the availability of open model libraries and virtual platform infrastructure. Leading communications, automotive, consumer electronics and embedded processor companies rely on Imperas for the development of their electronic products. The company’s corporate headquarters is located near Oxford, UK and it maintains support and sales organizations in Silicon Valley, California and Tokyo, Japan. For more information about Imperas, please go to www.imperas.com.

Imperas, Open Virtual Platforms, OVP, OVPsim, M*SDK, C*DEV, S*DEV, M*DEV, ToolMorphing and SlipStreamer are trademarks of Imperas Software Limited. Altera, Hardcopy and Nios words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries.  Imperas acknowledge trademarks or registered trademarks of other organizations for their respective products and services.

# # #

Imperas Provides Comprehensive ARM TrustZone Modeling Kit For OVP-Based Virtual Platforms

Kit Includes Modeling Application Note and Four Open Source, Executable Platform Examples Based Upon OVP™ ARM Cortex™ Processor Models With TrustZone Technology

OXFORD, United Kingdom, October 8th, 2013 – Imperas Software Ltd. (www.Imperas.com), a pioneer of advanced embedded software development systems using virtual platforms, today made available a System Modeling Kit designed to simplify the creation of high-performance virtual platforms that incorporate the ARM TrustZone technology.

The System Modeling Kit provides four open source virtual platform reference models, together with an application note and video, to demonstrate best modeling practices for systems based on TrustZone. The kit is designed to accelerate the learning curve for modeling TrustZone-based hardware, to provide high-performance, accurate virtual platforms that accelerate system verification, and make available immediate solutions for the execution of software stacks that incorporate security solutions based on TrustZone.

“TrustZone has become an important standard for the generation of secure embedded systems, and the Imperas OVP Fast Processor models of ARM cores that incorporate the technology are being leveraged by many of our leading customers,” noted Simon Davidmann, Founder and Chief Executive Officer of Imperas Software. “TrustZone can be complex, so we have made these reference solutions and guides public with the aim of accelerating the modeling of efficient virtual platforms that incorporate the technology.”

The ARM TrustZone technology provides a system-wide approach to security on high performance computing platforms for many applications, including secure payment, digital rights management (DRM), enterprise and web-based services. Integrated into specific ARM Cortex-A and ARM 11 processors, TrustZone extends throughout the system to secure components from software attack. Many electronic product companies are leveraging TrustZone in their development programs, proliferating this standard throughout the electronics industry.

The Open Virtual Platform (OVP) models of the ARM Cortex-A5, Cortex-A7, Cortex-A8, Cortex-A9, Cortex-A15 and ARM 11 processors all contain the TrustZone security extensions. The processor models are implemented using Imperas’ high performance code morphing technology to allow software engineers to execute code at hundreds of millions of instructions per second. Incorporated within the model, enabled by the unique ToolMorphing™ technology, is the Imperas range of advanced development tools for efficient software analysis and debug.

The Imperas TrustZone System Modeling Kit is available now, and may be downloaded from the OVP website www.OVPworld.org/tz_download. A comprehensive application note is available from www.OVPworld.org/tz_appsnote, and a video that walks through the application note and explains the examples running is available to watch here: www.OVPworld.org/tz_video. To execute the platform examples, a license is required for either the Imperas M*DEV or M*SDK products, available from Imperas.com.

About Imperas
Imperas Software Ltd was founded in 2008 to develop and deliver embedded software development systems. The company’s comprehensive product line enables the rapid creation of high-performance virtual platforms and the efficient development of embedded software utilizing those platforms. Imperas’ technology allows for software engineering schedules to be significantly reduced while improving the quality of products relying on embedded systems. In 2008 Imperas founded the Open Virtual Platforms (OVP) consortium to improve the availability of open source model libraries and virtual platform infrastructure. Leading communications, automotive, consumer electronics and embedded processor companies rely on Imperas for the development of their electronic products. The company’s corporate headquarters is located near Oxford, UK and it maintains support and sales organizations in Silicon Valley, California and Tokyo, Japan. For more information about Imperas, please go to www.imperas.com.

Imperas, Open Virtual Platforms, OVP, OVPsim, M*SDK, C*DEV, S*DEV, M*DEV, ToolMorphing and SlipStreamer are trademarks of Imperas Software Limited. ARM, the ARM Logo, Cortex, TrustZone and any other trademark found on the ARM trademarks list that are referred to or displayed in the document are trademarks or registered trademarks of ARM Ltd or its subsidiaries. Imperas acknowledge trademarks or registered trademarks of other organizations for their respective products and services.

# # #