NECs CyberWorkBench and Imperas OVP Fast Processor Models Integrated to Expand Hardware-Software Co-Verification Capabilities

OVP is De Facto Source for Fast Processor Models

OXFORD, United Kingdom, May 22, 2012 – Imperas today announced that its Open Virtual Platforms (OVP) OVPsim simulator and OVP Fast Processor Models have been integrated with NEC’s CyberWorkBench (CWB) SystemC cycle-accurate hardware models. OVP’s position as the de facto source of instruction accurate processor core models provides additional value to CyberWorkBench’s complete C/SystemC SoC design flow including ANSI-C/SystemC synthesis, hardware-software (HW/SW) co-verification and C-based formal verification.

CyberWorkBench is a C-based electronic circuit design platform developed by NEC over the course of twenty years. CyberWorkBench is developed around the “All-in-C” paradigm that allows high level synthesis and verification of any ANSI-C or SystemC program generating high quality circuits. CyberWorkBench also includes software co-simulation environments and source code debuggers.

OVP is widely used by our customers, who demanded the integration with CyberWorkBench. This integration significantly broadens CWB’s HW/SW co-verification support,” said Kazutoshi Wakabayashi, Senior Manager, Embedded Systems Solution Division, NEC. “We were also very impressed with Imperas technical support helping us achieve this integration extremely quickly and efficiently.

NEC will have demos showing the integrations available for users to watch at the upcoming Design Automation Conference (DAC) in San Francisco (booth #614).

All OVP processor models are instruction accurate, and very fast, focused on enabling embedded software developers, especially those building hardware-dependent software such as firmware and bare metal applications, to have a development environment available early to accelerate the software development cycle. Virtual platforms utilizing these OVP processor models can be created with the OVP peripheral and platform models, or the processor models can be integrated into SystemC/TLM-2.0 based virtual platforms using the native TLM-2.0 interface available with all OVP processor models. The OVP simulator also has integration into an Eclipse IDE, enabling easy use for software developers. In addition to working with the OVP simulator, these models work with the Imperas advanced tools for multicore software verification, analysis and debug, including key tools for software development on virtual platforms such as OS and CPU-aware tracing, profiling and code analysis.

NEC’s CyberWorkBench, with its comprehensive system level flow, represents the next step in SoC design methodology,” said Simon Davidmann, president and CEO, Imperas. “Imperas, by providing significant technology as Open Virtual Platforms, and creating a collaborative environment for tool vendors, IP developers, users and academics, is contributing to the evolution of a new embedded system design methodology.

In addition to working with the OVP simulator OVPsim, the OVP Fast Processor Models work with the Imperas Multiprocessor/Multicore/Multithread Software Development Kit (M*SDK). These advanced tools for multicore software verification and analysis include key tools for software development on virtual platforms such as OS and CPU-aware tracing (instruction, function, task, event), hot spot profiling, code coverage and memory and cache analysis. The M*VAP (Verification, Analysis and Profiling) tools utilize the Imperas SlipStreamer patent pending binary interception technology. SlipStreamer enables these analytical tools to operate without any modification or instrumentation of the software source code, i.e., the tools are completely non-intrusive.

About Imperas (www.Imperas.com)

For more information about Imperas, please go to the Imperas website.

About the Open Virtual Platforms Initiative (www.OVPworld.org)

For more information about OVP, please go to the About OVP page on the OVP website. Detailed quotations regarding OVP are available from http://www.ovpworld.org/quotes.

About NEC Corporation

NEC Corporation is a leader in the integration of IT and network technologies that benefit businesses and people around the world. By providing a combination of products and solutions that cross utilize the company’s experience and global resources, NEC’s advanced technologies meet the complex and ever-changing needs of its customers. NEC brings more than 100 years of expertise in technological innovation to empower people, businesses and society. For more information, visit NEC at www.nec.com.

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Open Virtual Platforms, OVP, OVPsim, SlipStreamer, M*SDK and M*VAP are trademarks of Imperas Software Limited. Imperas acknowledges trademarks or registered trademarks of other organizations for their respective products and services.

Imperas paper voted in top 5 at Cadence CDNlive users meeting

Cooley’s CDNlive’12 Trip Report lists best papers. Fast Processor Models comes 4th

At the recent Cadence CDNlive event there were 95 papers presented and the conference attendees vote as to which papers they rate the best.

Imperas’ Larry Lapides presented a paper on Fast Processor Models for SystemC Virtual Platforms and we were surprised and pleased that it was rated 4th best paper – the event is traditionally focused on silicon design, and yes the top 3 papers were related to that. So it just goes to show that the adoption of virtual platforms is becoming more and more important.

The paper introduced why multicore/multiprocessor software development fails using old techniques, and explains that initial usage of virtual platforms with multiple debuggers and multiple windows just made everything more painful. “No wonder that more than half of current embedded design projects are behind schedule …”.

The paper discussed SystemC Virtual Platforms and introduced the Imperas OVP Fast Processor Models, how they are constructed, used, and what is available.

The paper continued by discussing the library of models ranging from all the ARM Classic thru Cortex, the MIPS full range, Renesas, Xilinx, etc, and then explored use models based on the Cadence Virtual System Platform model of the Xilinx Zynq-7000 EPP using the Imperas OVP Fast Processor Model of the ARM Cortex-A9MPx2 core. The paper concluded by introducing some of the Imperas advanced software tools.

If you would like more information on the Imperas paper, please contact us at info@imperas.com.

More information on CDNlive can be found here.

More information on John Cooley’s trip report can be found here. Scan down for ‘Best Papers’.

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Fast Processor Models of MIPS Technologies New Aptiv Generation Cores Released by Imperas and Open Virtual Platforms

OVP Fast Processor Models Developed Under MIPS-Verified(tm) Program

OXFORD, United Kingdom, May 10, 2012 – Imperas(tm) is releasing the Open Virtual Platforms(tm) (OVP(tm)) Fast Processor Models for MIPS Technologies new Aptiv(tm) Generation of processor cores. Example virtual platforms are also being released, as well as support for the cores in Imperas M*SDK(tm) advanced software development tools. MIPS Technologies has verified the functionality of the Aptiv models under the MIPS-Verified(tm) program.”

The processor core models and example platforms are available from the Open Virtual Platforms website, http://www.OVPworld.org/MIPS. The models of the Aptiv processor cores, as well as models of other MIPS(R) processors, work with the Imperas and OVP simulators, and have shown exceptionally fast performance of hundreds of millions of instructions per second.

Our new Aptiv Generation of cores pushes the boundaries in performance and efficiency. Having MIPS-Verified support from Imperas and OVP, a leading supplier of high-quality, fast processor core models, enables our customers to get started immediately with designs based on the Aptiv Generation cores,” said Giddy Intrater, vice president of marketing, MIPS Technologies. .

All OVP processor models are instruction accurate, and very fast, focused on enabling embedded software developers, especially those building hardware-dependent software such as firmware and bare metal applications, to have a development environment available early to accelerate the software development cycle. Virtual platforms utilizing these OVP processor models can be created with the OVP peripheral and platform models, or the processor models can be integrated into SystemC/TLM-2.0 based virtual platforms using the native TLM-2.0 interface available with all OVP processor models. The OVP simulator also has integration into an Eclipse IDE, enabling easy use for software developers. In addition to working with the OVP simulator, these models work with the Imperas advanced tools for multicore software verification, analysis and debug, including key tools for software development on virtual platforms such as OS and CPU-aware tracing, profiling and code analysis.

The OVP library of Fast Processor Models includes the complete families of the ARMv4, ARMv5, and ARMv6 architecture-based processors, as well as models of most of the processors in the ARM Cortex-M series and Cortex-A series processors. In addition to working with the OVP simulator, these models work with the Imperas Multiprocessor/Multicore Software Development Kit, M*SDK, which includes advanced tools for multicore software verification, analysis and debug, including key tools for software development on virtual platforms such as OS and CPU-aware tracing, profiling and code analysis.

State of the art processor cores, especially multicore processors, such as these new Aptiv cores from MIPS require state of the art software development tools,” said Simon Davidmann, president and CEO, Imperas and founding director of the OVP initiative. “OVP Fast Processor Models, which are faster, more accurate and easier to use than other models, accelerates the development cycle and makes debug and optimization easier for software engineers.

OVP offers MIPS developers access to all of the MIPS32(R) 32-bit processor models, including the MIPS32 4K, 24K, 34K, 74K, 1004K, 1074K and M14K families of cores. OVP also has reference virtual platforms incorporating the MIPS cores, including bare metal platforms and a virtual platform of the MIPS Malta development board. This Malta virtual platform enables users to boot Linux in under 5 seconds on a 2GHz laptop using OVPsim, and to boot multicore SMP (Symmetric Multi-Processor) Linux in less than 8 seconds. These reference platforms are all available as source code, and are easily modified to add or change the memory and peripheral components to customize the platform as required for software development.

In addition to working with the OVP simulator OVPsim, the OVP Fast Processor Models work with the Imperas Multiprocessor/Multicore/Multithread Software Development Kit (M*SDK). These advanced tools for multicore software verification and analysis include key tools for software development on virtual platforms such as OS and CPU-aware tracing (instruction, function, task, event), hot spot profiling, code coverage and memory and cache analysis. The M*VAP (Verification, Analysis and Profiling) tools utilize the Imperas SlipStreamer(tm) patent pending binary interception technology. SlipStreamer enables these analytical tools to operate without any modification or instrumentation of the software source code, i.e., the tools are completely non-intrusive.

About Imperas (www.Imperas.com)

For more information about Imperas, please go to the Imperas website.

About the Open Virtual Platforms Initiative (www.OVPworld.org)

For more information about OVP, please go to the About OVP page on the OVP website. Detailed quotations regarding OVP are available from http://www.ovpworld.org/quotes.

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Open Virtual Platforms, OVP, OVPsim, SlipStreamer, M*SDK and M*VAP are trademarks of Imperas Software Limited. Imperas acknowledges trademarks or registered trademarks of other organizations for their respective products and services.